Dummy metals and dummy vias were used in integrated circuits, for example, for reducing micro-loading effects in the manufacturing processes. In existing methodology for inserting dummy metals and dummy vias, metal lines and metal vias are laid out first, and the dummy metals and dummy vias are inserted to chip areas that are not used by the metal lines and metal vias. The existing insertion methodology may suffer from low insertion efficiency.
Accordingly, there is a need for an improved method to provide insertion methodology with high insertion efficiency.